@2016-07-02 新版功能: 创建
在 @2019-02-13 版更改: 添加内存分类
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- UDIMM: Unbuffered DIMM. Unbuffered, low density, low-latency DIMM that doesn't include a register or buffer chip. Generally used in applications requiring the lowest possible latency.
- RDIMM: Registered DIMM. Registered DIMM that provides high signal integrity (performing parity checking to detect improper addresses or commands) and increased performance for heavy workloads. RDIMMs experience slightly increased latency and power consumption over UDIMMs due to the onboard register.
- LRDIMM: Uses a buffer to reduce memory loading to a single load on all DDR signals, allowing for greater density.
- Standard Voltage (SV) DDR3 operates at 1.5 volts which is currently required for 1600 million transfers per second (MT/s)
- Low Voltage (LV) DDR3 operates at 1.35 volts or 1.5 volts. At 1.35 volts the memory can consume less power and reduce heat, but can still be boosted to 1.5V when the memory channel requires additional voltage to help maintain maximum speed.
- Advanced ECC mode (otherwise known as lockstep mode) uses two memory channels and "ties" them together to emulate a 128-bit data bus DIMM. This is primarily used to achieve Single Device Data Correction (SDDC) for DIMMs based on x8 DRAM technology. SDDC is supported with x4 based DIMMs in every memory mode.
- Memory Optimized mode (or Independent Channel mode) allows memory channels to run independently of each other; for example, one can be idle, one can be performing a write operation, and the other can be preparing for a read operation. Memory may be installed in one, two, three, or four channels. To fully realize the performance benefit of the memory optimized mode, all four channels per physical processor should be populated.
- Memory Mirroring mode allows memory to be "mirrored" from one channel into a paired channel. This provides 100% memory redundancy, but cuts the available memory to the operating system in half in addition to halving the available memory controllers and channels. This will have a direct impact on memory bandwidth, which should see less than half the memory bandwidth as compared to memory Optimized mode. This will have seriously negative performance implications, and should only be considered for applications that require mission critical levels of memory RAS.
- Memory Rank Sparing mode reserves a memory rank as a spare as long as there are at least 2 DIMMs or 4 ranks available in a memory channel. If a memory rank experiences a high number of correctable errors above a certain threshold, the memory controller will swap the failing rank with the spare rank. The spare rank is invisible to the operating system, thus overall memory available to the operating system is decreased.
对 Dell 服务器，详细信息参考 Dell PowerEdge: Server Memory Configuration 。